1. Field of the Invention
The present invention relates to data processing systems in general and more particularly to interrupt systems for handling priority interrupt requests.
2. Prior Art
The processor in a typical data processing installation is often called upon to perform sundry tasks and/or events within the installation. The tasks may be external and/or internal to the processor. External tasks are usually associated with external events. Such events may include the reading of external sensors, accepting data from a communication channel, etc. Internal tasks may include sampling a condition following the expiration of an internal counter, etc.
In addition to the named tasks, the processor usually performs functions (sometimes called background functions) when its service is not required to handle the named tasks.
A typical processor usually operates at electronic speed. As such, it requires relatively short time intervals to complete assigned tasks. Similarly, it can perform a large number of tasks within a very short time interval. Notwithstanding its speed, the processor is a serial device. It can only perform a single task during a particular time interval. There are several tasks that require immediate attention once the vent that triggers the condition occurs. For example, real time peripherals usually require prompt attention. The situation is even more complicated because most real time peripherals run asynchronously to the execution of background code. This means the processor cannot predict the exact time when these devices require servicing.
To improve the versatility of the processor, an interrupt system is provided. The interrupt system includes several prioritized interrupt levels. A user usually assigns one or more events to one of the interrupt levels. Whenever the event occurs, an interupt request is raised. Depending on the level of the interrupt, the processor will either continue to execute the code it was executing at the time the new interrupt occurs or temporarily cease to process the code and branches to the new code that has to be executed in order to service the new interrupt. If the interrupt request is on a higher level than the one which is being executed, the processor branches and runs the new code. Following its completion, the processor returns to run the code from which it branches (i.e., the old code). On the other hand, if the interrupt request is on the same or lower level as the one which is being executed, the processor queues the interrupt request and continues to run the current code. Because of the immediate nature of some events, queueing is not an acceptable solution. It is the queueing problem that the present invention seeks to correct.
The prior art describes several interrupt systems. All of the disclosed systems and/or schemes are aimed at improving the efficiency of a processor to handle interrupts. For example, U.S. Pat. Nos. 4,001,783; 4,028,664; 4,172,284 and 3,905,025 set forth several devices and techniques for prioritizing the servicing of events on different interrupt levels of a processor interrupt heirarchy.
Still other prior art patents such as U.S. Pat. Nos. 4,456,970 and 4,459,657 set forth techniques and devices that allow a processor to branch from the code that services a low level priority event to the new code that services a high level priority event.